Luceda Photonics IPKISS Design Suite 2025.12 is the latest major version of the comprehensive photonic integrated circuit (PIC) design platform from Luceda Photonics. Built around IPKISS—a powerful parametric design framework in Python—it enables designers to create, simulate, layout, and verify photonic circuits with full control over geometry, simulation, and tape-out preparation. This release empowers PIC designers to work more efficiently, collaborate seamlessly, and gain deeper insights from the earliest design stages through streamlined PDK creation, interactive visualization, smarter placement & routing, native dummy fill support, and enhanced simulation robustness.
The platform integrates layout (IPKISS Canvas), circuit simulation (Caphe), physical simulation (via PDKs and solvers), verification, and fabrication prep in one ecosystem, supporting foundry PDKs (SiFab, open-source, commercial) and enabling rapid prototyping to production-ready GDSII/OA exports.
Key Features of Luceda Photonics IPKISS Design Suite 2025.12
- Easy PDK Creation & Building: New guided wizard in the Luceda Control Center to launch a New Design Kit Project; quickly generates a structured PDK skeleton with layers, component library, automated documentation, and built-in validation routines; supports automatic building of distributable packages (docs, layer files, schematic IPKISS Canvas files, OpenAccess libraries).
- Interactive Signal Tracer: Brand-new tool for real-time visualization of light propagation in PIC layouts; trace optical signals through waveguides, components, and circuits; helps debug connectivity, losses, and behavior interactively.
- Enhanced Placement & Routing (P&R): Smarter automation with length matching for waveguide connectors (i3.MatchLength intelligently shifts control points to equalize path lengths); new placement features (e.g., i3.Distribute for uniform instance distribution); improved Manhattan connectors and control point handling for faster, more precise routing.
- Native Dummy Fill Support: Direct dummy fill insertion inside IPKISS layouts (i3.dummy_fill_layout) while designing; post-process existing GDSII files (i3.dummy_fill_gdsii); simplifies tape-out preparation and DRC compliance without external tools.
- Tape-out Preparation & DRC Fixes: New step-by-step tutorial on fixing DRC violations; streamlined verification workflows to ensure fabrication-ready PIC designs.
- Upgraded Layout Visualizer: Enhanced navigation and inspection with new visual aids (anchor highlighting, cell hierarchy browsing); better overview of complex layouts for quicker reviews.
- Easy Design Sharing & Collaboration: Improved export/share mechanisms for interactive designs (viewable without full license); supports team workflows and stakeholder reviews.
- Simulation Robustness: General improvements in simulation accuracy and performance; better handling of complex photonic circuits and PDK-based solvers.
- General Platform Enhancements: Modernized UI, better error diagnostics, and workflow refinements; full Python-based parametric design with PCells, Caphe circuit simulation, and layout-to-GDSII flow.
